Computer systems which can use an array of processors which can execute programs in parallel have been developed.
VLSI technology can now place multiple processors (each with its own memory) on either a single chip or multiple chips in very close proximity. Such parallel arrays of processors can be configured into either Single Instruction Steam Multiple Data Stream (SIMD), or Multiple Instruction Stream Multiple Data Stream (MIMD), or Single Instruction Stream Single Data Stream (SISD) configurations, but to date, neither multiple types of modes have been employed, and there has been no machine which has provided a form where the mode can be changed dynamically and efficiently during program execution.
Some of the work appears to have be based in part on my book entitled "The Architecture of Pipelined Computers", published by Hemisphere Publishing Corporation in 1981 under ISBN 0-89116-494-4. This work has an historical perspective which still is useful after a decade of progress in the field, see pages 11-20.
There continue to be developments in the field of different mode oriented machines. For example for the SIMD mode, recently U.S. Pat. No. 4,992,933 entitled SIMD ARRAY PROCESSOR WITH GLOBAL INSTRUCTION CONTROL AND REPROGRAMMABLE INSTRUCTION DECODER issued on Feb. 12, 1991 to James L. Taylor with respect to an array processor which provided a multi-dimensional array of processing elements and which provided a mechanism where the processing elements may be simultaneously updated in a SIMD fashion in response to a global load instruction which forces an interrupt to all processing elements.
Most advanced machines today are MIMD. U.S. Pat. No. 4,916,652 issued to Schwarz and Vassiliadis on Apr. 10, 1990 and entitled DYNAMIC MULTIPLE INSTRUCTION STREAM MULTIPLE DATA MULTIPLE PIPELINE APPARATUS FOR FLOATING POINT SINGLE INSTRUCTION STREAM SINGLE DATA ARCHITECTURES addresses implementing a MIMD machine via multiple functional pipelines, and interleaving the different instruction streams into these pipelines. This patent contemplated switching the machine from MIMD to SISD for a shod period of time to handle some complex instruction for floating point operation.
There are others which have interrupted the MIMD mode of a machine. U.S. Pat. No. 4,873,626 issued Oct. 10, 1989 and U.S. Pat. No. 4,891,787 issued Jan. 2, 1990, both to David K. Gifford, describe a Parallel MIMD processing system with a processor array having a SIMD/MIMD instruction processing system. These two patents define a single CPU that is an overall controller to multiple groups of processors (PEs) and memories, where each group has an interconnection path of some sort. A parallel bus interconnects the master CPU to the groups. This machine has proved that all PEs can be running independant program code in MIMD fashion. Like the other above patent there is the capability of interrupting the processing of the PEs which are controlled by the single Master Control Processor.
Currently, most SIMD processors (e.g. the Connection Machine CM-2) are either stand alone units, or operate as a front end or back end of an MIMD mainframe. Each processor is established to perform a specific function, and schemes like those which require interrupts require a substantial amount of overhead to perform limited specialized mode operations. However, most computer algorithms or programs may have some strong match to efficient parallel execution in one of several modes (SIMD or MIMD). Furthermore, virtually all algorithms would benefit from a machine architecture that permitted different modes of execution for different pads of a problem. The existing proposals have not adequately addressed this need.